Through the system design and test of the scheme, the feasibility of the practical application of the POE chip combined with the network switch is demonstrated. The scheme is complete in design and stable in operation, and can fully meet the normal operation of various types of powered devices of the back-end network.
I. Introduction
POE (Power Over Ethernet) Power over Ethernet refers to the existing Ethernet Cat.5 cabling infrastructure without any changes, for some IP-based terminal devices (such as IP phones, wireless LAN access points) APs, network cameras, etc., while transmitting data signals, can also provide DC power supply technology for such devices. The POE equipment includes the power output device PSE and the power receiving device PD. This paper focuses on the power output device PSE.
With POE technology, users no longer need to provide wall power for each POE connected terminal device, saving the need for connecting IP phones, wireless LAN access points, video surveillance cameras, building management systems and remote video kiosks. Power wiring costs.
In addition, with PoE, enterprises can also lock some key equipment on one power supply and support the whole system with UPS backup power supply. As a result, the entire system's power supply guarantee will be greatly improved, thus improving the reliability of the entire system equipment. safety.
Second, the system follows the standards
With the increasing use of Ethernet in the world, the corresponding networking equipment has been rapidly developed. In the long-term use, the supporting power supply has always been one of the bottlenecks that have further plagued the terminal equipment of the networking. Thus, the standard for powering Ethernet devices through Ethernet data line pairs or alternate pairs is naturally enforced with market demand and technology development.
The IEEE 802.3af standard specifies the Power over Ethernet (POE) and related implementation details. As a power transmission protocol based on Ethernet, the standard specifies the mechanism for the corresponding power transmitting equipment (PSE) to supply power to the powered device (PD). It includes implementation rules for online testing, hierarchical processing, power-on, and disconnection protection for powered devices. The protocol also specifies the Ethernet Transmission Line (PTL).
The system scheme of this paper is completely based on the above standards. The system ensures the normal operation of the existing network while ensuring the security of the existing structured cabling, thus minimizing the cost.
Third, chip selection and circuit design
Before the system design, we compared a number of chips that can realize PSE function in the world. The MAX5980 of American Maxim has attracted our attention because of its excellent design, reasonable supporting scheme and smooth flow of the entire control channel. This is playing a vital role in our future design.
The MAX5980 is a four-channel power-supply device (PSE) power controller. The chip is specifically designed for use with IEEE 802.3at/af and compatible PSE devices.
According to the requirements of the standard, the device has functions such as detection, classification, current limiting, and load disconnection detection for the back-end powered devices. The device supports fully automated operation while supporting software programming control. The device also supports new two-event grading and Category 5 detection and grading capabilities for high-power powered devices.
The device supports single-supply operation, and each port (Category 5 enabled) delivers up to 70W of power while providing high-capacity immunity to the back-end legacy powered devices.
According to the technical characteristics of the MAX5980, we first designed an electrical schematic of a 4-way PSE, as shown in Figure 1.
According to the chip data, the input voltage of the PSE controller MAX5980 is designed to be 48V DC. The output part of the chip uses four high-power FETs as the current control terminals of the four network power outputs.
The 48V DC input is provided by a switching power supply. The power is output through the network port and is provided to the powered device at the back end. The FET is a key component in the control loop of the entire power supply output. The source of the FET in the loop is connected to a 0.25 ohm sampling resistor and then returned to the chip.
The output current is passed through a FET and sampled by a sampling resistor to monitor the current in the output loop. The chip can be sampled at any time via the SENSE port to read the load characteristics of the back-end PD device. After judging, the chip can control the G-pole of the FET to make various control responses.
According to the definition of the 802.3at protocol and the functional design of the chip, the chip will judge according to different sampling data, and then perform detection, classification, port voltage start, overcurrent protection, undervoltage and overvoltage protection. Thereby achieving the operation of the entire chip system.
During the debugging process, two 0.1uf capacitors are connected to the 48V input terminal to suppress the ripple coefficient of the power supply, enhance the anti-interference ability, and improve the reliability of the power supply. At the same time, the SMIB58 transient suppression tube is also selected at the 48V terminal to prevent the impact of large current and avoid damage to the device.
The 1, 2, and 3 pins of the MAX5980 are external serial bus interface lines. The I2C serial bus is not used in this article. These three wires must be grounded according to the design literature requirements.
The 5, 6, 7, and 8 pins of the chip serve as the position-coding end of the slave address of the device and must be grounded in the design.
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