In the traditional control system, people often use single chip microcomputer as the control core. However, this method has complicated hardware wiring and poor reliability, and the number of MCU ports, internal timers, and interrupt sources are limited. In actual applications, an expansion chip is often required. This undoubtedly brings a lot of inconvenience to the system design.
Many systems now use programmable logic devices CPLD as the control core. Compared with the traditional design, it not only simplifies the interface and control, improves the overall performance and working reliability of the system, but also creates conditions for system integration. However, the D flip-flop resources of programmable logic devices are very limited, and programmable logic devices are not as convenient as microcontrollers in controlling timing. Many unfamiliar users often feel very difficult to apply. The two-way communication controller composed of programmable logic devices and single chip computers overcomes the shortcomings of the two, and maximizes the advantages of the two.
1 CPLD and single chip AT89C51 two-way serial communication principle
1.1 Serial communication from single chip microcomputer to programmable logic device
The serial communication interface circuit from MCU to CPLD is to design an eight-bit shift register with serial input and parallel output in CPLD using VHDL language, and its port is connected with P1.4 ～ P1.7 of MCU, as shown in Figure 1. CS is the single-chip selection signal, when it is low, the eight-bit register is enabled; when the rising edge of the DCLOCK signal reaches the clk port, the eight-bit shift register will shift the one-bit data output from the single-chip computer to cxin; when the single-chip A register When the eight-bit data in is to be transmitted to CPLD, eight rising edges are generated continuously at P1.6, and the single-chip microcomputer will sequentially move the data in A to cxin, and the data segment in A will appear in CPLD after eight times. Cxout.
The VHDL source program is as follows:
enTIty cuanxing is
port (clk, cxin, cs: in std_logic;
cxout: out std_logic_vector (7 downto 0));
end;
architecture rtl of cuanxing is
signal shift: std_logic_vector (7 downto 0); parallel output of eight temporary storage variables
begin
process (clk)
begin
if (cs = '0') then
shift <= (others => '0'); if not selected, output all zeros
elsif (clk'event and clk = '1') then; If the rising edge reaches clk, it is selected.
shift (7 downto 1) <= shift (6 downto 0); shift the eight-bit data one bit forward
shift (0) <= cxin; the lowest bit is input by cxin
end if;
end process;
cxout <= shift; send the eight-bit variable to the port
end rtl;
The corresponding MCU control subroutine is as follows (data to be sent are stored in A):
CS EQU P1.4
EN EQU P1.5
DCLOCK EQU P1.6
DOUT EQU P1.7
CONV: PUSH 07H
MOV R7, # 8; store the shift number 8 in R7
CLR DCLOCK
SETB CS; select shift register
CLR EN
CLR C
JXL: RLC A; shift one bit to the left to send the data to be sent to CY
MOV DOUT, C; sent to the port
ACALL YS1MS
SETB DCLOCK; give a rising edge, move the data into the shift register
ACALL YS1MS
CLR DCLOCK
DJNZ R7, JXL; if it is less than 8 times, send the next one
SETB EN; all eight-bit command words are shifted in, giving EN a rising edge to make CPLD perform corresponding operations
ACALL YS1MS
POP 07H
RET
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