Various IP Core and reference designs
The following various IP Core and reference designs are provided by related designers and can be downloaded for free to learn or use.
[Precautions for use]
Most designs are designed for a specific device, developed on a specific software platform, and need to be changed when porting to other software platforms or devices. When using these codes, be sure to read the relevant information carefully, use them after reading the source code, or modify or redesign your own design, porting to other platforms without understanding the source code, there will be many error. (This column was updated on April 14, 2003)
Asynchronous communication interface (URAT)
| UART 1 | UART reference design with 16byte buffer, provided by Xilinx | manual | VHDL code |
| UART 2 | UART reference design, compatible with NS16450, provided by LatTIce | manual | VHDL code |
| UART 4 | UART reference design, provided by Xilinx | manual | VHDL code Verilog code |
| 6850 | a6850 asynchronous communication interface, compatible with MC6850 altera | manual | VHDL code |
16450 | 16450 asynchronous communication interface, provided by ALDEC | manual | VHDL code Verilog code |
16450 | 16450 asynchronous communication interface, provided by ALDEC, revised version (modified by netizen zhy, to correct some errors, please refer to the file notes for details) | Verilog code |
Processors and peripherals
| 8237 | 8237 programmable DMA controller provided by altera | manual | VHDL code |
| 8237 | 8237 programmable DMA controller ALDEC provides | manual | VHDL code |
| 8251 | a8251 programmable communication interface provided by altera | manual | VHDL code |
| 8255 | a8255 programmable peripheral interface, officially certified, provided by altera | manual | VHDL code |
| 8255 | 8255 programmable peripheral interface, provided by ALDEC | manual | VHDL code |
| 8259 | a8259 programmable interrupt control provided by altera | manual | VHDL code |
| 8259 | 8259 Programmable interrupt control provided by ALDEC | manual | VHDL code |
| 8051 interface | PLD and 8051 interface reference design Xilinx provides | manual | VHDL code |
| PopCorn | A streamlined CPU with 8-bit CISC structure, 2 also provides a compiler | download | |
| 8051 | 8051 reference design, compared with other 8051 free IP, the documentation is relatively complete, provided by Oregano System | manual | VHDL code |
| IDE | ATA/IDE interface controller, provided by opencore  | manual | Code |
| USB2.0 | USB2.0 interface, provided by opencore, for reference only | verilog code | |
| I2C | I2C bus controller altera provides | manual | VHDL code |
| I2C | I2C bus controller Xilinx provides | manual | VHDL code |
| I2C | I2C code provided by Opencore | HDL code | |
| CAN interface | CAN bus controller | Verilog code | |
| SMBus | SMBus controller Xilinx provides | manual | VHDL code |
| SPI interface | Serial Peripheral Interface Master (Serial Peripheral Interface Master) Provided by Xilinx | manual | VHDL code |
| USB interface | USB interface controller reference design, provided by xilinx | manual | VHDL code |
| PCI interface | 32-bit/33M slave mode (target) PCI interface reference design, provided by LatTIce. Due to the complexity of PCI timing, this design is for reference only | manual | Verilog code |
| PCI arbitration | PCI bus arbitration reference design, provided by Quicklogic | manual | Verilog code |
SDR SDRAM controller 1 | Standard SRD SDRAM controller reference design, provided by altera | manual | VHDL code Verilog code | |
| SDR SDRAM controller 2 | Standard SRD SDRAM controller reference design, provided by xilinx | manual | VHDL code Verilog code | |
| SDR SDRAM controller 3 | Standard SDR SDRAM controller reference design, provided by LatTIce | manual | Vrilog code | |
| SDR SDRAM Controller 4 | The SDRAM controller reference design is slightly different from the above. It was originally designed for MACH devices. Provided by LatTIce | manual | VHDL code Verilog code | |
| DDR SDRAM controller 1 | DDR (dual rate) SDRAM controller reference design, provided by altera | manual | VHDL code Verilog code | |
| DDR SDRAM controller 2 | DDR (dual rate) SDRAM controller reference design, provided by xilinx | manual | Verilog code | |
| ZBT SRAM controller 1 | ZBT SRAM controller reference design, provided by xilinx, (ZBT SRAM is a high-speed synchronous SRAM) | manual | VHDL code Verilog code | |
| ZBT SRAM controller 2 | ZBT SRAM controller reference design, designed for APEXII devices, provided by altera, automatically installed after downloading, see installation instructions for details | manual | VHDL code | |
| FCRAM controller | FCRAM controller xilinx provides | manual | ||
| Flash interface | Flash interface controller xilinx provides | manual | verilog | |
| FFT | A paper using VHDL to implement fast Fourier transform, including principle analysis and code implementation, provided by MA College, Mahatma Gandhi University, India | manual | VHDL code |
| 16-point FFT | 16-point fast Fourier transform FFT, 16-bit data input/output, provided by xilinx | manual | VHDL code |
| 1024 point FFT | 1024-point FFT fast Fourier transform, 16-bit data input/output, with DMA function, provided by xilinx | manual | VHDL code |
| logarithm | You can calculate the logarithm based on 2, 10, and e. Add the license to the original MaxplusII or QuartusII license and you can use it directly, but the source code is encrypted. provided by altera | manual | Logarithmic IP |
| Square root | The IP for hardware solving the square root can be used directly by adding the license to the original MaxplusII or QuartusII license, but the source code is encrypted. provided by altera | manual | Square root IP |
| Basic mathematical operation library | Including various basic mathematical operation units described in VHDL language, provided by the Swedish Federal Institute of Technology (ETH) | Instructions for use 1 2 | VHDL mathematical operation library 1.0 |
| CRC check code automatic generation tool | Automatically generate VHDL or verilog source programs of various CRCs according to input conditions | manual | Run online | |
| CRC check reference design | IEEE 802.3 Cyclic Redundancy Check reference design, provided by xilinx | manual | Verilog code | |
| CRC check reference design | Configurable CRC reference design provided by xilinx | manual | VHDL code and description | |
| A rate/u rate compression | A rate/u rate compression and decompression IP core can be used directly by adding the license to the original MaxplusII or QuartusII license, but the source code is encrypted. provided by altera | A/u rate compression and decompression | ||
| 16B/20B codec | 16B/20B codec provided by Xilinx | manual | ||
| DDS | Direct frequency synthesis, provided by Quicklogic, some of the source files are special files for Quicklogic | manual | Verilog code | |
| Manchester codec | Manchester codec provided by Xilinx | manual | VHDL code Verilog code | |
| 1553 codec | MIL-STD-1553 encoding and decoding provided by Lattice | Verilog code and documentation | |
| Serial-to-parallel conversion | Convert multiple synchronous serial data streams into parallel data through a multi-channel serial-to-parallel converter provided by xilinx | manual | HDL code download |
| Keyboard scan | Keyboard scanning program, provided by xilinx, design file is opened with ISE | manual | Design file download |
| DES | High-speed DES and 3DES encryption and decryption reference design provided by Xilinx | ||
| Chromaticity space transformation | Color Space Converter (RGB to YCbC) Provided by Xilinx | manual | VHDL/Verilog |
| LFSR code automatic generation tool v1.2 | The linear feedback shift register (LFSR) is an important circuit structure in the digital system. This program can automatically generate codes and circuit schematics for AHDL, VHDL, and Verilog. Users who are not sure about LFSR can read this article first | manual | |
General purpose memory | Includes VHDL descriptions of various types of memory, such as FIFO, dual-port RAM, etc. | VHDL code base |
| FreeCore Library 1 | Free AHDL module library, including 28 modules such as IIC controller, DRAM controller, UART, AHDL source code | ||
| FreeCore Library 2 | Includes 9 free VHDL/VerilogHDL reference designs, such as SDRAM controllers, etc. (Updated in August 2002!) | ||
| Free-IP core | Provide several VHDL free IP Cores, such as RAM, CPU, etc. | ||
| Opencore | An organization dedicated to the development of open IP cores provides engineers with some free IP, such as PCI, etc., but many cores are only for reference, and there may be some problems if they have not been fully tested. | ||
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